1. Field of the Invention
This invention relates to low power designs for application specific integrated circuits (hereinafter xe2x80x9cASICxe2x80x9d), and more particularly to a system and method for designing ASIC devices that are optimized for power.
2. Background of the Invention
Low power designs in electronic systems are becoming increasingly more important as personal and mobile devices, such as laptop computers and cellular phones, become more popular. Because battery life represents a critical limitation in such devices, the importance of providing low power designs has become an important design constraint. Incorporated into many of today""s electronic systems are powerful ASIC devices designed to provide a high degree of functionality for a particular device or type of application. As such, ASIC""s tend to be large consumers of power. Unfortunately, traditional tools for designing integrated circuits (IC""s) often do not consider power reduction to be as critical as other design criteria, such as area and speed. Accordingly, today""s design tools lack the sophistication to adequately optimize an ASIC device for power reduction.
ASIC""s are logic chips designed by the end-customers to perform a specific function and thereby meet the specific needs of their application. Customers implement their designs in a single silicon die by mapping their functions to a set of predesigned, preverified logic circuits provided by the ASIC vendor. These circuits are referred to as the ASIC vendor""s library, and are described in the ASIC vendor""s databook. These circuits range from the simplest functions, such as inverters, NANDs and NORs, flip-flops and latches, to more complex structures such as static memory arrays, adders, counters and phase-lock loops. Recently vendors have added some highly complex circuits to their ASIC libraries, such as microprocessors, Ethernet(copyright) functions, and peripheral component interconnect (PCI) controllers.
The process of creating a lower power ASIC design is currently a manual one aided by various software tools. The logic designer typically studies node toggle and power calculation reports and makes architectural or structural changes to the high level netlist to quiet down or turn off areas of the design that do not need to be powered up at all times. This is typically done by shutting off the clocks to certain regions of the design or holding previous data steady when a change in data is not required for proper functioning of the ASIC.
In recognition of this problem, ASIC software tool vendors are starting to address this area of low power design with different tools to evaluate design power. One method uses a dynamic gate-level power simulator that models non-linear power consumption behavior. Other tools perform a gate level power analysis for making quick estimates during synthesis process. A paper entitled: xe2x80x9cWhat Is The State Of The Art In Commercial EDA Tools For Low Power,xe2x80x9d by Coudert, Haddad and Keutzer, of Synopsys, Inc., ISLPED 1996 Monterey, Calif. USA, discusses such methods and is hereby incorporated by reference.
Unfortunately, none of these tools take a dynamic approach to power optimization. Specifically, none recognize the fact that typical ASIC designs, such as those designed for embedded systems, are built to execute a relatively well defined set of applications (i.e., program instructions) stored in read only memory (TOM). Thus, no known methods exist for designing power optimized ASIC devices based on the applications that will likely run on the ASIC.
The present invention provides a system and method for dynamically optimizing ASIC designs to reduce power consumption. The present invention recognizes the fact that the toggling of nets between states (e.g., high to low) directly correlates to power consumption. To identify frequently toggling nets, the present invention simulates the operation of an ASIC design with a set of applications similar to those that will eventually run on the ASIC device. The output of the simulation comprises net toggle information, which details how often each net toggles during typical usage of the ASIC. The simulation process also includes a mechanism for weighting each of the applications such that more frequently used applications are given more weight when determining the net toggle information.
The net toggle information may be utilized at two different stages of the design process. First, net toggle information may be generated at the behavioral or RTL (register transfer level) design levels, when the ASIC design is represented in a high level logic language such as VHDL (VHSIC Hardware Description Language) or Verilog. By performing simulations as described above, fundamental architectural modifications to reduce power consumption can be implemented by the designer based on the net toggle information. Secondly, net toggle information can be generated at the gate design level, after the ASIC design has been synthesized and physically laid out. The net toggle information generated at the gate level, together with physically extracted net capacitance and RC delay data, can then be fed back into the synthesis process to optimize the ASIC for power reduction. This process can be repeated until an acceptable design is achieved.
It is therefore an advantage of the present invention to provide weighted net toggle information.
It is therefore a further advantage of the present invention to provide a system for dynamically designing an ASIC device using feedback data that profiles the likely operation of the ASIC device.
It is therefore a further advantage of the present invention to provide a method and system for reducing power consumption in an ASIC device.